Voltage controlled oscillators (VCOs) are phase locked for applications in VHF, UHF and microwave frequency ranges. Typical applications of such phase locked oscillators are abundant in the field of communication systems technology and radar applications as stable, low-phase noise signal sources.
Both digital and analog phase lock techniques are known. Digital phase locking can, for example, be achieved by using a frequency divider to divide a high frequency of a VCO to a lower frequency of a crystal reference. Such a technique is useful at low frequencies down to about 1 MHz, but can also be used at higher frequencies up to and beyond 3 GHz. A limitation of these devices is their phase noise characteristics. An example of a phase locked loop realized in digital form has been described, for example in U.S. Pat. No. 5,061,904 to Mantopoulos et al.
Analog phase locking of oscillators can be achieved using a sampling phase detector (SPD), see for example “Theory and Application of Sampling Phase Detector, Application Note APN5001”, from Skyworks Solutions, Inc., dated Jul. 21, 2005, where it is described how the SPD can be used for phase locking a dielectric resonator Oscillator (DRO). U.S. Pat. No. 6,753,704 B1 to Desgrez et al. describes an example of an analog sampling phase detector.
Such techniques are generally attractive because of the low phase noise levels that are achievable in such circuits.
A limitation of the SPLO (Sampling Phase Locked Oscillator) solution has been the limitations in frequency selection as only integer times the reference frequency could be generated.
Hence it is an objective of the present invention to provide a phase locked oscillator with a wider choice available in the choice of output frequency than has previously been possible.